1. Field of the Invention
The present invention relates to integrated circuit memory devices and, more particularly, to an electrically-erasable programmable read only memory (EEPROM) storage cell having EPROM-type programming suitable for use in a programmable logic array (PLA).
2. Discussion of the Prior Art
More efficient utilization of device area in very large scale integration (VLSI) technology is a prominent objective in order to increase the density, and thus increase the number of memory cells on a semiconductor chip for reducing costs and increasing speed of operation. In particular, there has been much investigation into non-volatile memory devices (i.e., a type of memory device that retains stored data even after power to the device has been removed).
An electrically programmable ROM (EPROM) implements non-volatile storage of data using a storage transistor having a so-called floating gate. The floating gate is located between a control gate and a substrate, and (unlike the control gate) is not connected to a word, bit, or any other line; it "floats." The EPROM is programmed by having hot electrons injected into the floating gate to cause a substantial shift in the threshold voltage of the storage transistor. Under high gate and high drain voltages, electrons gain sufficient energy to jump the silicon-silicon dioxide energy barrier, penetrating the oxide and flowing to the floating gate, which is completely surrounded by oxide. The injected electrons cause a 5 to 10 volt increase in the threshold of the device, changing it from an ON to an OFF state when a nominal 5 volt read voltage is applied to the control gate. That is, if the floating gate holds electrons, it is negatively charged. The negative electric field developed by the floating gate counteracts the positive field applied on the control gate (assuming an NMOS device). Thus, an activated word line cannot generate a sufficiently strong field using the control gate to turn-on the transistor. This type of storage transistor is known in the art as a Floating gate Avalanche injection MOS (FAMOS) device. A significant problem associated with the FAMOS structure generally employed in EPROM devices is that in order to erase the data, the chip must be exposed to ultraviolet (UV) radiation to remove the charge carriers from the floating gate. In-system erasability is thus not possible with such a structure.
Electrically-erasable programmable read only memory (EEPROM) devices have been developed to overcome, to some extent, the above-mentioned problem associated with the FAMOS structure used in EPROM devices. The basic operation of a conventional Floating gate Tunnel OXide (FLOTOX) EEPROM memory cell is well-known. In a FLOTOX cell, the tunnel oxide, which is generally less than 100 .ANG. thick, is formed over a portion of the drain region. The FLOTOX cell is designed such that a large fraction of the applied voltage is coupled across the tunnel oxide. Programming the FLOTOX cell requires application of a gate field.gtoreq. about 10.sup.7 v /cm such that the well-known Fowler-Nordheim tunneling of electrons through the tunnel oxide to the floating gate will occur. Such an electric field is conventionally obtained by grounding both the source and the drain, and applying a high voltage V.sub.pp to the control gate of the FLOTOX transistor. The tunnelled charge shifts the threshold voltage of the transistor.
Erasing the cell is achieved by grounding the control gate, floating the source and applying a high voltage to the drain. In this case, most of the applied voltage is coupled across the tunnel oxide, but the field is reversed, resulting in tunneling of electrons from the floating gate to the drain.
FIG. 1 shows a prior art EEPROM memory cell 10, which will be used to clearly illustrate the shortcomings of the prior art. Cell 10 includes a high voltage access transistor 12, tunnel oxide 14, floating gate 16, buried control gate 18, low voltage access transistor 20, and a read transistor 22 that shares floating gate 16. Operation of cell 10 may be understood by those skilled in the art with reference to the following table:
TABLE 1 ______________________________________ SINGLE POLY EEPROM CELL SCHEMATIC HV BL LV BL PA PB WL ______________________________________ PROGRAM Vpp-Vth Vcc Vss Vss Vpp ERASE Vss Vcc Vpp Vss Vpp READ Vss 2.0 Vss Vss Vcc ______________________________________
HV BL refers to a high voltage bit line, LV BL refers to a low voltage bit line, PA refers to phase A of a clock, PB refers to phase B of the clock, and WL refers to a word line of the cell. Cell 10 is representative of the prior art--it is a single poly design--only the floating gate 16 is of polycrystalline silicon material. As is known in the art, transistor 12 is included in cell 10 in order to isolate the tunnel oxide 14/floating gate 16 from the high voltage on HV BL when cell 10 is in an unselected state. It should be appreciated that transistor 12, in order to withstand conventional high voltages on HV BL (e.g., 15 volts), includes source and drain junctions of special design (i.e., much wider diffusion pitches). Accordingly, a memory cell having such a high voltage transistor incurs a significant size penalty and further, is not readily amenable to scaling. Finally, due to the manner in which transistor 12 is constructed, it further suffers in terms of reliability (i.e., due to various "steps" in the oxide layers).
Another problem with the single poly EEPROM cell 10 is the use of a buried control gate, as shown at 18. Such a configuration requires a tremendous amount of device area. Finally, not unlike other prior art E.sup.2 PROM memory cells using Fowler-Nordheim emission through a runnel oxide for programming, cell 10 is characterized by a relatively slow (e.g., 10 milliseconds) programming speed.
Accordingly, there is a need to provide an improved memory structure suitable for use in a memory device, such as a flash memory device, that minimizes or eliminates one or more of the problems as set forth above.